Method of making N-channel and P-channel IGFETs with different g

Details Method of making N-channel and P-channel IGFETs with different g Method of making N-channel and P-channel IGFETs with different g

1998-02-02

1999-10-05

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438197, 438275, 257368, 257369, 257371, H01L 2702, H01L 218238

Patent

active

059638036

ABSTRACT:
A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region. Preferably, the N-channel device is formed in the first active region, the P-channel device is formed in the second active region, and the N-channel and P-channel devices include lightly and heavily doped source and drain regions. In this manner, the relatively thick gate for the P-channel device reduces boron penetration, and the relatively wide spacers for the P-channel device offset the rapid diffusion of boron in the heavily doped source and drain regions of the P-channel device during high temperature processing so that the lightly doped source and drain regions for the N-channel and P-channel devices have the desired sizes.

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Silicon Processing for the VLSI Era--vol. 3: The Submicron MOSFET by Stanley Wolf, Lattice Press, Sunset Beach, CA, 1995, pp. 311-313 and 641-643.
U.S. Patent Application Serial No.: 08/844,925, filed Apr. 21, 1997, entitled Method of Making Enhancement-Mode and Depletion -Mode IGFETs with Different Gate Thicknesses, by Gardner et al.

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