Memory data bus architecture and method of configuring multi-wid

Details Memory data bus architecture and method of configuring multi-wid Memory data bus architecture and method of configuring multi-wid

1998-12-14

2000-04-11

Dinh, Son T.

Static information storage and retrieval

Addressing

Plural blocks or banks

365207, 365208, G11C 800

Patent

active

060495014

ABSTRACT:
A memory device (50) contains a first array of memory (12) and a second array of memory (14). The arrays (12 and 14) are coupled to four segmented current data buses (iGDLs) (16, 18, 20, and 22). When in a x36 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate directly with output buffers (56-59) through several current-to-voltage converters (24-31). When in a x18 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate through the converts (24-31), through a voltage bus (52 and 54, see also FIG. 3), to the output buffers (56-59). The change in wiring for x36 word mode versus x18 word mode is done either by a top-level metal option in fabrication or by user software programming whereby the device (50) is easily wired into one of two configurations while maintaining an advantageous speed/power product.

REFERENCES:
patent: 5555215 (1996-09-01), Nakagome et al.
patent: 5821792 (1998-10-01), Miwa
patent: 5825709 (1998-10-01), Kobayashi
patent: 5835437 (1998-11-01), Omachi

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