Row redundancy circuit suitable for high density semiconductor m

Details Row redundancy circuit suitable for high density semiconductor m Row redundancy circuit suitable for high density semiconductor m

1993-11-23

1995-11-21

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523006, 371 103, G11C 2900, G11C 700

Patent

active

054693888

ABSTRACT:
A semiconductor memory device has a plurality of memory cell arrays, each with a normal cell array and a spare cell array. Fuse circuits are programmable to substitute a spare-cell-array word line for a defective word line in any normal cell array. When a defective word line is addressed, a fuse circuit activates a spare-cell-array word line, and also activates a redundancy signal line. A single redundancy signal line is shared by all fuse circuits and block select circuits. Block select circuits normally enable the cell array that includes the defective word line, however, the block select circuits are disabled when the defective word line has been replaced by a spare word line an another block.

REFERENCES:
patent: 5257229 (1993-10-01), McClure et al.
patent: 5265055 (1993-11-01), Horiguchi et al.

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