Current limited epld array

Details Current limited epld array Current limited epld array

1987-01-22

1988-11-15

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, G11C 700, G11C 1134

Patent

active

047854235

ABSTRACT:
An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between "on" and "off" states which results in an improved speed performance of the device.

REFERENCES:
patent: 4371956 (1983-02-01), Maeda et al.

Affiliated with

Also associated with

Rating

Current limited epld array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current limited epld array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current limited epld array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1107414