MOS output buffer circuit with controlled current source

Details MOS output buffer circuit with controlled current source MOS output buffer circuit with controlled current source

1993-09-17

1995-01-31

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 83, 326112, H03K 190175, H03K 19017

Patent

active

053861574

ABSTRACT:
An integrated buffer circuit configuration has two inverters which are mutually connected in series. The first inverter includes an n-channel transistor and a constant current source. The source of the n-channel transistor is connected to a first supply potential. The drain of the transistor is connected with the constant current source through a first enable transistor. A second enable transistor is connected parallel to the constant current source. The gates of enable transistors are connected with the enable input of the buffer circuit. An enable signal present at the enable input makes it possible to deactivate the buffer circuit in the case of disturbances with a known course over time. A MOS transistor may function as the constant current source. The MOS transistor is then connected to a second supply potential and its gate lies at reference potential with a value with always has a constant difference with respect to the second supply potential. During operation, the MOS transistor is conducting.

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patent: 5036227 (1991-07-01), Jo et al.
patent: 5051625 (1991-09-01), Ikeda et al.
patent: 5194764 (1993-03-01), Yano et al.
patent: 5268599 (1993-12-01), Matsui

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