Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1987-03-18
1989-02-07
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365205, 365206, 365207, 365194, G11C 700, G11C 1140, H03K 524
Patent
active
048036633
ABSTRACT:
A dynamic RAM having a plurality of pairs of folded bit lines each divided into a plurality of pairs of divided bit lines comprises transfer gates (QT1, QT2) provided for each pair of divided bit lines for connecting/disconnecting the pair of adjacent divided bit lines to each other, sense amplifiers (SA1, SA2) provided for each of the pairs of divided bit lines for detecting and amplifying potential difference between the pairs of divided bit lines, restore circuits (RE1, RE2) provided for each of the pairs of divided bit lines for boosting the potential on the bit line on the side of a high potential of the pairs of the divided bit lines, and a control circuit (TG) for turning the transfer gates (QT1, QT2) on after a predetermined time since the sense amplifier was operated in response to a sense amplifier activating signal.
REFERENCES:
patent: 4255678 (1981-03-01), Suzuki et al.
patent: 4451906 (1984-05-01), Ikeda
patent: 4545037 (1985-10-01), Nakano
Digest of Technical Papers, ISSCC 84, "A Sub 100ns 256K DRAM in CMOS III Technology", by R. I. Kung et al., pp. 278-279.
Miyamoto Hiroshi
Yamada Michihiro
Bowler Alyssa H.
Hecker Stuart N.
Mitsubishi Denki & Kabushiki Kaisha
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