Planarization technique for DRAM cell capacitor electrode

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438255, H01L 218242

Patent

active

060109319

ABSTRACT:
A method of forming a DRAM includes forming a transfer FET on a substrate, the FET having a gate on a gate oxide layer above the substrate and a first and second source/drain region in the substrate on either side of a channel region under the gate. The first and second source/drain regions are typically exposed or nearly exposed in a spacer etch process. A silicon nitride etch stop layer is deposited over the entire structure and then a thick layer of oxide is deposited on the device. Chemical mechanical polishing is performed to provide a planar surface on the thick oxide layer. An opening is formed through the thick layer of oxide above the first source/drain region, stopping at the etch stop layer. The etch stop layer is removed within the opening in the thick layer of oxide and the underlying thin oxide layer is etched. A capacitor electrode can then be formed in contact with the exposed portion of the first source/drain region. A similar self-aligned method can be used to form the bit line contact for the device using the etch stop layer as a stop for the bit line contact etch. Practice of the method provides a manufacturing method having improved reliability and ease of use, particularly when practiced for DRAM capacitors that incorporate high dielectric constant dielectrics. The materials preferred for use within such DRAM capacitors have smaller process margins and so particularly benefit from the improved structure and process.

REFERENCES:
patent: 5501998 (1996-03-01), Chen
patent: 5668036 (1997-09-01), Sune
patent: 5702989 (1997-12-01), Wang et al.
patent: 5770498 (1998-06-01), Becker
patent: 5843818 (1998-12-01), Joo et al.

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