Method of making asymmetrical transistor structures

Details Method of making asymmetrical transistor structures Method of making asymmetrical transistor structures

1998-09-30

2000-09-19

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438307, 438945, H01L 21336

Patent

active

061210935

ABSTRACT:
A method of forming an asymmetric transistor and an asymmetric transistor. The method includes patterning a first spacer material and a second spacer material over a gate electrode material on a substrate with one side of the second spacer material adjacent to a first spacer material. The gate electrode material is patterned according to the first spacer material and the second material. Junction regions are formed in the substrate adjacent to the gate electrode material. One of the first spacer material and the second spacer material is then removed and the gate electrode material is patterned into a gate electrode according to the other of the first spacer and the second spacer material. Finally, second junction regions are formed in the substrate adjacent to gate electrode.

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F. Wang, Y. Shi, J. Liu, Y. Lu, S. Gu & Y Zheng, "High Selective Chemical Etching of Si vs. Si.sub.1-x Ge.sub.x Using NH.sub.4 OH Solution," J. Electrochem. Soc., vol. 144, No. 3, Mar. 1997, pp.L37-L39.
T.K. Carns, M.O. Tanner & K.L. Wang, "Chemical Etching of Si.sub.1-x Ge.sub.x in HF:H.sub.2 O.sub.2 :CH.sub.3 C00H," J. Electrochem. Soc. vol. 142, No. 4, Apr. 1995, pp. 1260-1266.

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