Semiconductor processing methods of forming hemispherical grain

Details Semiconductor processing methods of forming hemispherical grain Semiconductor processing methods of forming hemispherical grain

Filed on

2000-01-27

Date issued

2000-09-19

Examiner

Smith, Matthew

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

438398, 438260, 438239, H01L 21302

Type

Patent

Status

active

Patent number

061210846

Description

ABSTRACT:
In one aspect of the invention, an amorphous layer of silicon is provided which has a gradient of thickness variation. The amorphous layer of silicon is transformed into a hemispherical grain polysilicon layer that has varying grain size therein. In another aspect of the invention, a material is provided and has an upper surface and inwardly tapered openings. A first electrically conductive electrode layer is formed within the openings and includes a plurality of hemispherical grain polysilicon layers. At least one of the hemispherical grain polysilicon layers has a grain size gradient defined by a smaller grain size in a region proximate the upper surface and a larger grain size beneath the region with the smaller grain size. An electrically insulative layer is formed over the first electrode layer and a second electrically conductive electrode layer is formed over the electrically insulative layer.

REFERENCES:
patent: 5831282 (1998-11-01), Nuttall
patent: 5840606 (1998-11-01), Lee
patent: 5877061 (1999-03-01), Halle et al.
patent: 5930641 (1999-07-01), Pan
patent: 6025225 (2000-02-01), Forbes et al.
patent: 6046083 (2000-04-01), Lin et al.
patent: 6066529 (2000-05-01), Lin et al.

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