Method for preventing damage to gate oxide from well in compleme

Details Method for preventing damage to gate oxide from well in compleme Method for preventing damage to gate oxide from well in compleme

1998-08-25

2000-05-09

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438666, 438675, 438189, H01L 218238

Patent

active

06060347&

ABSTRACT:
A method for preventing damage to a gate oxide layer from a floating well in a CMOS device includes a first via plug and a second via plug formed in a dielectric layer. The first via plug is coupled to a substrate and the second via plug is coupled to the well. These two via plugs are further coupled by a conductive bridge so that both the well and the substrate have the same voltage.

REFERENCES:
patent: 5350710 (1994-09-01), Hong et al.
patent: 5393701 (1995-02-01), Ko et al.
patent: 5514623 (1996-05-01), Ko et al.
patent: 5650745 (1997-07-01), Merrlii et al.
patent: 5817577 (1998-10-01), Ko

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