Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1991-03-04
1991-11-12
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36523008, 365233, G11C 800
Patent
active
050653652
ABSTRACT:
A dynamic random access memory, which includes a data input buffer, a data input latch circuit, a data output buffer, and a switching circuit. For example, in an operation in a read-write cycle, at first, a data signal to be written is stored in the latch circuit 7 concurrent with inputting of an address signal in response to a signal WE. A data signal read from a memory cell is output via the output buffer in response to a signal OE. The switching circuit is turned on, and the data signal which has been latched is provided to the memory cell via a pair of I/O lines. As a result, the time required for the operation in the read-write cycle is shortened.
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Hecker Stuart N.
Mitsubishi Denki & Kabushiki Kaisha
Whitfield Michael A.
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