Zeroing circuit for performance counter

Details Zeroing circuit for performance counter Zeroing circuit for performance counter

2003-08-06

2008-09-30

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S706000

Reexamination Certificate

active

07430696

ABSTRACT:
In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits (“MSBs”) of a selected portion of the debug data based on a mask generated by a mask generator block. A selection control signal provided to the mask generator block is operable to be decoded to a particular mask.

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