Zero-write-cycle memory cell apparatus

Details Zero-write-cycle memory cell apparatus Zero-write-cycle memory cell apparatus

1997-03-28

1998-09-15

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 36518901, 36518911, G11C 1100

Patent

active

058089330

ABSTRACT:
A zero-write-cycle memory cell apparatus for simultaneously reading and writing data to and from a memory cell via isolated read and write wordlines wherein read cycles operate without dedicated write cycles. The zero-write-cycle memory cell apparatus includes a memory cell or storage circuit for the storage of binary data and a write circuit for writing binary data to the memory cell or storage circuit wherein the write circuit includes a write wordline. The presence of a binary data signal at the write wordline optimizes write performance independently of a read path from the memory cell. The zero-write-cycle memory cell apparatus further includes a read circuit for reading binary data from the memory cell or storage circuit. The read circuit includes a read wordline. The presence of a binary data signal at the read wordline optimizes read performance independently of a write path into said memory cell. The zero-write-cycle memory cell apparatus additionally includes a write-enable device, coupled to the memory cell or storage circuit, for providing a write-enable signal to the memory cell. The write-enable circuit can be shared by other memory cells to form a memory array. The zero-write-cycle memory cell apparatus is designed such that dedicated write cycles do not occur, only dedicated read cycles.

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