Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-06-29
2002-10-01
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S225700, C365S205000, C365S196000
Reexamination Certificate
active
06459637
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to semiconductor memory devices and, more particularly, to an apparatus and method for controlling a time point at which a sense amplifier is enabled in a semiconductor memory device. The invention allows for a zero margin to be obtained in software regarding the enabling time point of the sense amplifier.
2. Background Description
In general, when a semiconductor memory device executes a read operation, a word line is enabled and, after a constant time, a sense amplifier (hereinafter also referred to as “S/A”) is enabled to read cell data. However, it cannot be surely guaranteed that the stored cell data is sufficiently developed to a local data line at a time point when the sense amplifier is enabled. In other words, the word line and a sense amplifier enable signal are not exactly in synchronization. As used herein, the term “margin” corresponds to a difference between a time point or time period when data stored in a cell is sufficiently developed to a local data line (i.e., a current or voltage representative of the data is within a predefined threshold) and a time point or time period when the sense amplifier that “senses” the data is enabled. Moreover, as used herein, the phrase “zero margin” refers to when the preceding defined difference is substantially equal to zero (the local data line and the sense amplifier enable signal are in synchronization). Most semiconductor memory devices include a unit that is capable of controlling an enable of the sense amplifier disposed therein. In general, a fuse option is used. When an appropriate enabling time point of the sense amplifier is determined by the cutting of a fuse(s) during the initial product development, the enabling time point is used without change when there are no problems with the operating speed of the product.
FIG. 1
is a diagram illustrating an enable controlling apparatus of a conventional sense amplifier. The apparatus includes a row address decoder
10
, a tracking unit
20
, and a fuse array
30
. A word line is activated when a row address and a block address are simultaneously selected, and an S/A enable signal is activated with the block address and a fuse array signal. A time point of the S/A enable signal is controlled by cutting a fuse of the fuse array
30
. However, if the fuse cutting is controlled, the enabling time point of the sense amplifier for a corresponding chip is always fixed.
In the case of a plurality of chips, if there is a characteristic difference between each of the chips, the same cutting of the fuse array in all of the chips poses a problem in that the enabling time point of the sense amplifier is not optimized for each chip. In particular, when the operating speed of the semiconductor memory device barely satisfies a target operating speed, the conventional cutting system for the fuse array is not desirable. In this case, an evaluation period for an initial product is increased and a chip is consumed for the sake of the evaluation. Accordingly, there is a need for an apparatus and method for controlling a time point at which a sense amplifier is enabled in a semiconductor memory device that overcomes the above-described problems of the prior art.
SUMMARY OF THE INVENTION
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a zero margin enable controlling apparatus and method of a sense amplifier in a semiconductor memory device. Advantageously, the present invention determines an optimum enabling time point of the sense amplifier on a per chip basis, and cuts fuses in accordance therewith. Moreover, the present invention determines an optimum enabling time point of the sense amplifier using software.
According to an aspect of the invention, there is provided an apparatus for controlling an enable of a sense amplifier in a semiconductor memory device. The apparatus includes a test part for repeatedly varying a test code value until the enable of the sense amplifier has a zero margin with respect to data to be read by the sense amplifier, and for determining the test code value at a time point when the enable has the zero margin. A fuse array cuts a fuse corresponding to the determined test code value.
According to another aspect of the present invention, there is provided a method for controlling an enable of a sense amplifier in a semiconductor memory device. The semiconductor memory device has a test part and a fuse array. The test part determines a zero margin enabling time point of the sense amplifier through a test that uses a variable code. The method includes the step of executing the test by varying a time point of the enable of the sense amplifier until the enable has a zero margin with respect to data to be read by the sense amplifier. A corresponding fuse is cut that is representative of a code value used at the time point when the enable has the zero margin in said executing step.
These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 5245578 (1993-09-01), McLaury
patent: 5712477 (1998-01-01), Delaney et al.
Lee Jong-Cheol
Lee Kwang-Jin
F. Chau & Associates LLP
Ho Hoai
Le Thong
Samsung Electronics Co,. Ltd.
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