Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2005-03-29
2005-03-29
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S233100, C365S185110, C365S185290
Reexamination Certificate
active
06873564
ABSTRACT:
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. A data buffer is coupled to data communication connections to manage the bi-directional data communication. Finally, a write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. One method of operating a synchronous memory device comprises receiving write data on data connections, latching the write data in a write latch, and releasing the data connections after the write data is latched. A read operation can be performed on the synchronous memory device while the write data is transferred from the write latch to memory cells. Further, the memory device does not require any clock latency during a write operation.
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Leffert Jay & Polglaze PA
Micro)n Technology, Inc.
Phan Trong
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