Programmable delay circuit within a content addressable memory

Details Programmable delay circuit within a content addressable memory Programmable delay circuit within a content addressable memory

2005-03-08

2005-03-08

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S049130, C365S233100, C365S189050, C365S189070, C365S189020, C365S230060, C327S149000, C327S161000, C711S128000, C711S167000

Reexamination Certificate

active

06865121

ABSTRACT:
An apparatus including a content addressable memory (CAM) array, a clocked circuit coupled to the CAM array, and a programmable delay circuit coupled to receive a reference clock signal and generate a programmable delayed clock signal using a delay element for the clocked circuit. The CAM array may include a plurality of rows of CAM cells each having a corresponding match line for carrying a match signal indicative of whether comparand data matches data of the corresponding row of CAM cells.

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