Zero clock delay metastability filtering circuit

Details Zero clock delay metastability filtering circuit Zero clock delay metastability filtering circuit

2007-10-30

2007-10-30

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

C327S024000

Reexamination Certificate

active

11397570

ABSTRACT:
A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge detection circuit coupled to the sampling circuit for receiving the sampled first clock signal and for producing a rate adapted first clock signal; a delay circuit coupled to the edge detection circuit for receiving the rate adapted first clock signal and for producing first and second clock enable signals, the second clock enable signal being a delayed version of the first clock enable signal; and, a shift register clocked by the second clock signal and having first and second sequential registers enabled by the first and second clock enable signals, respectively, for receiving an input signal from the first system at the first register and providing a filtered output signal to the second system from the second register, wherein the filtered output signal is provided within one cycle of the first clock signal thereby providing zero clock delay between the input and filtered output signals.

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