Yield profile manipulator

Details Yield profile manipulator Yield profile manipulator

2004-03-16

2008-07-01

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07395522

ABSTRACT:
A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.

REFERENCES:
patent: 6809802 (2004-10-01), Tsukamoto et al.
patent: 2004/0126004 (2004-07-01), Kikuchi
patent: 2005/0146714 (2005-07-01), Kitamura et al.
patent: 2005/0190349 (2005-09-01), Leroux
patent: 2006/0033917 (2006-02-01), Leroux et al.
patent: 2007/0072091 (2007-03-01), Smith et al.

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