Yield maximization in the manufacture of integrated circuits

Details Yield maximization in the manufacture of integrated circuits Yield maximization in the manufacture of integrated circuits

2005-10-18

2005-10-18

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06957402

ABSTRACT:
A method and apparatus for improving the manufacturability of Integrated Circuits (ICs) formed on semiconductor dies is described. A plurality of different designs for some or all of the standard cells are made available to the circuit designer. Each different design may address a different problem associated with different manufacturing processes or a different design related yield limiter. Each of the design variants is characterized indicating its relative ease of manufacture, or it's yield sensitivity to certain IC design factors. The designer, typically with assistance from computer aided tools, can then select the standard cell variant for each of the cell used in the IC design that best addresses his or her design constraints. In other embodiments, variant versions of I/O cells and memory cells could also be created and made available to the designer in a similar fashion.

REFERENCES:
patent: 6418353 (2002-07-01), Rostoker et al.
patent: 6539533 (2003-03-01), Brown et al.
patent: 6745371 (2004-06-01), Konstadinidis et al.
patent: 2002/0091979 (2002-07-01), Cooke et al.
patent: 2003/0188268 (2003-10-01), Konstadinidis et al.
patent: 2004/0143797 (2004-07-01), Nguyen et al.

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