Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Yield
Reexamination Certificate
2008-11-03
2011-11-01
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Yield
C716S136000, C716S112000
Reexamination Certificate
active
08051394
ABSTRACT:
A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.
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Chen Ji-Jan
Chen Jwu-E
Cheng Liang-Chia
Luo Pei-Wen
Wey Chin-Long
Dimyan Magid
Industrial Technology Research Institute
Jianq Chyun IP Office
National Central University
Whitmore Stacy
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