Y-mux splitting scheme

Details Y-mux splitting scheme Y-mux splitting scheme

2006-08-29

2006-08-29

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189020

Reexamination Certificate

active

07099202

ABSTRACT:
A multiplexer circuit in a memory organized into page-portions has a plurality of bit-select multiplexers configured to couple a plurality of page-portion global bitlines to a sense amplifier input. A plurality of column address lines organized into data bytes comprises each page-portion. A plurality of column multiplexers couple the data bytes to the page-portion global bitlines such that each of the address lines comprising the data byte is coupled to one of the page-portion global bitlines.

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