Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-08-22
2001-11-06
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S713000, C438S737000, C438S738000, C438S978000
Reexamination Certificate
active
06313019
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a method for forming a gate structure with a contact area wider than a base area.
BACKGROUND OF THE INVENTION
Historically, gate structures having a base area with a width that is smaller than the gate contact area (e.g., T-gate and Y-gate structures) have been advantageous in several technologies. For example, MESFET, HEMT (variant of gallium arsenide field effect transistor technology) mainly used in satellite broadcasting receivers, high speed logic circuits and power modules have employed gate structures with bases smaller than the contact area. These types of devices are required in field effect transistors for operation in ultra-high frequency ranges. The advantage of employing a gate structure with a shorter gate length is that the channel of the gate is reduced resulting in an increased in speed and a decrease in power consumption. Reducing the distance over which the gate's field effect control of the electrons in the channel reduces the parasitic resistances and capacitances that limit device speed. A shorter gate length decreases the transmit time for carriers in the channel but also increases the series resistance of the gate electrode itself, slowing down the device and degrading the frequency characteristics of the device. Providing a gate structure with a smaller base than its contact area decreases the gate channel while providing a low gate series resistance due to the wider contact area and, thus, improving the devices drive current capability and performance.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Recent advances in CMOS transistor architecture make use of the T-gate or Y-gate structures where the polysilicon gate electrode is narrowed in the gate regions and wider on top of the gate. This is due to the ever increasing demand for scaling down semiconductor devices and scaling down power consumption requirements. However, the current methods for forming a gate structure with a contact region wider than its base suffers from shortcomings. For example, the etch process which narrows the base of the structure are known to be difficult to control especially with local pattern density. This can lead to variation in the gate width and asymmetric implant profiles. Another problem is related to manufacturing controls. The “re-entrant” or overhung profile prevents direct measurement of the critical gate length.
In view of the above, there is an unmet need for improvements in methodologies for formation of gate structures with contact areas that are wider than the base area.
SUMMARY OF THE INVENTION
One aspect of the invention relates to a method for fabricating a Y-gate structure comprising the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer and portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed.
Another aspect of the present invention relates to another method for fabricating a Y-gate structure. A silicon layer is provided having a gate oxide layer, a protection layer over the gate oxide layer, the protection layer being one of a polysilicon and a germanium material, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer. The contact material is the other of a polysilicon material and a germanium material. Portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed. Finally, portions of the protection layer and the gate oxide layer not forming a part of the Y-gate structure are removed.
Yet another aspect of the present invention provides for yet another method for fabricating a Y-gate structure. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer, a second sacrificial layer over the first sacrificial layer and a third sacrificial layer over the second sacrificial layer. The second sacrificial layer is of a different material than the first and third sacrificial layers. A first opening is vertically etched in the third sacrificial layer. An angular etch is performed on the first opening to provide an inwardly sloping opening in the second sacrificial layer. The inwardly sloping opening is an extension of the first opening. The first opening and the inwardly sloping opening are vertically etched to extend the opening vertically in the first sacrificial layer. A contact material is then provided to fill the first opening. The first sacrificial layer, the second sacrificial layer and the third sacrificial layer are stripped and portions of the protection layer and the gate oxide layer not forming a part of the Y-gate structure are etched away using one of a wet etch and a vertical plasma etch.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 4980316 (1990-12-01), Huebner
patent: 5155053 (1992-10-01), Atkinson
patent: 5677089 (1997-10-01), Park et al.
patent: 5801094 (1998-09-01), Yew et al.
patent: 5930610 (1999-0
Lyons Christopher F.
Plat Marina
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices
Amin & Turocy LLP
Dang Trung
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