XE preamorphizing implantation

Details XE preamorphizing implantation XE preamorphizing implantation

2001-08-01

2003-09-23

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S306000, C438S308000, C438S162000, C438S163000, C438S166000

Reexamination Certificate

active

06624037

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to manufacturing semiconductor devices, particularly highly miniaturized semiconductor devices having ultra-shallow junction depths.
BACKGROUND ART
The semiconductor manufacturing techniques undergo constant challenges as design features continue to plunge deeper into the submicron regime, as in fabricating devices having a design rule of about 0.12 micron and under. The accurate formation of ultra-shallow junction depths (X
j
) having high reliability in an efficient manner poses a particularly challenging problem.
Preamorphization techniques, as by ion implanting silicon (Si) or germanium (Ge), to define the contours of source/drain regions prior to dopant implantation and annealing have been employed to reduce the channeling effect and reduce transient enhanced diffusion (TED), and to reduce the activation temperature. Such preamorphization (SPE) techniques, however, are not without disadvantageous consequences. For example, implanted Si and Ge ions tend to migrate beyond the intended source/drain regions resulting in what is referred to as implantation straggle, both vertically and horizontally, making it extremely difficult to precisely define ultra-shallow source/drain extensions, e.g., below 400 Å.
As the design rules plunge into the deep sub-micron range, the channel length, i.e., distance between junctions across the channel, evolves as a critical dimension, particularly as the channel length is reduced to about 1000 Å and under. Natural variations in junction position as well as variations arising from processing render it difficult to accurately design devices. Alteration of a doping profile from TED as well as implantation straggle exacerbate design problems.
Conventional silicon-on-insulator (SOI) types of substrates have evolved and basically comprise a substrate, a buried oxide layer thereon, and a semiconductor layer on the buried oxide layer which constitutes the “body” of the transistor. In such SOI devices, the body floats in that there is no direct electrical connection to it. As the source and drain regions are isolated from the substrate, junction capacitance is reduced, i.e., when an electrical signal changes on either or both source and drain, there is significantly less capacitive coupling to the substrate. As electrical isolation is facilitated employing an SOI substrate, certain electrical elements of the circuit can be positioned closer together, thereby reducing the die size. SOI structures also offer the advantage of more rapid switching. In addition, latchup, which typically occurs in standard CMOS devices, does not exist employing SOI substrates, since the substrate is isolated by the buried oxide. Static or plasma arcing is also reduced in SOI derives.
There are, however, disadvantages attendant upon employing SOI substrates in fabricating semiconductor devices. A notable disadvantage is what is referred to as “floating body effects”. For example, it takes a considerable period of time for an ejected charge to leak out. As a result, transient bipolar effects can occur wherein a parasitic bypolar transistor turns on parallel to the MOSFET. In addition, hysteresis effects can occur.
There exists a need for efficient methodology to fabricate semiconductor devices having accurate ultra-shallow junctions. There also exists a need for efficient methodology to fabricate semiconductor devices having accurate ultra-shallow junctions based upon SOI substrates without floating body effects.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device having an SOI structure with reduced floating body effects.
Another advantage of the present invention is a method of manufacturing a semiconductor device having ultra-shallow junctions and accurately formed source/drain extensions and regions.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a silicon-on-insulator (SOI) structure comprising: a lower silicon substrate; a buried insulating layer on the substrate; and an upper layer of crystalline silicon on the insulating layer; ion implanting xenon (Xe) into the upper silicon layer to form an amorphous region therein extending from an upper surface toward the buried insulating layer; ion implanting dopant impurities to form source/drain extension implants and source/drain implants; and annealing to activate shallow source/drain extensions and source/drain regions, and to crystallize the amorphous region.
Embodiments of the present invention comprise forming an SOI structure with a silicon oxide buried insulating layer, ion implanting Xe at an implantation dosage of about 1×10
14
to about 5×10
14
ions/cm
2
and an implantation energy of about 1 KeV to about 200 KeV. Embodiments of the present invention comprise annealing at a temperature of about 500° C. to about 650° C., e.g., about 550° C. to about 600° C., to activate source/drain extensions and, the source/drain regions, and to recrystallize amorphous regions caused by Xe ion implantation. Embodiments of the present invention include forming the source/drain extensions prior to forming the source/drain regions, and also include removable spacer techniques wherein the source/drain regions are formed prior to the source/drain extensions.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprising: providing an ion beam consisting essentially of xenon dimer (Xe
2
+
); implanting the Xe
2
+
into a crystalline semiconductor substrate to form an amporhous region therein; ion implanting dopant impurities into the amorphous region to form source/drain extensions and source/drain implants; and annealing to activate the source/drain extensions and source/drain regions, and to recrystallize the amorphous region.
Embodiments include analyzing a first Xe ion beam and selectively extracting the Xe
2
+
beam therefrom. Embodiments of the present invention comprise ion implanting the Xe
2
+
into a substrate, inclusive of bulk silicon and SOI substrates, to preamorphize regions prior to ion implanting dopant impurities, followed by annealing at a temperature of about 500° C. to about 650° C. Embodiments of the present invention comprise ion implanting Xe
2
+
into a bulk silicon substrate forming amorphous regions having a depth no greater than about 250 Å, e.g., to about 100 Å to about 250 Å; and then forming source/drain extensions and source/drain regions with intermediate annealings at a temperature of about 500° C. to about 650° C.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
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patent: 5953615 (1999-09-01), Yu
patent: 6074937 (2000-06-01), Pramanick et al.
patent: 6191012 (2001-02-01), Ng et al.
patent: 6225176 (2001-05-01), Yu
patent: 6403433 (2002-06-01), Yu et al.

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