X-and-OR memory array

Details X-and-OR memory array X-and-OR memory array

1983-01-10

1986-07-22

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365189, 365230, G11C 1300

Patent

active

046023542

ABSTRACT:
A read-only memory array formed from a multiplicity of NAND-organized FET stacks which are arranged in pairs and connected in alternate succession of adjacent pairs at opposite ends. Selection of stacks by pairs is performed by connecting the common node of four stacks at one end to a bit line and the common node of another four stacks, only two being common with the former four stacks, to ground potential. Selection between adjacent stack pairs is performed by bank select FETs in each stack. Each stack is precharged at both ends prior to selection. A sense amp is utilized to compare the current sinking capacity of the selected bit line with a reference stack, the difference being detected in a differential amplifier. A programmable output driver provides an adjustable rate of change in the output signal for step input signals.

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patent: 4489400 (1984-12-01), Southerland, Jr.
Kitano et al., "A 4Mb Full Wafer ROM", 1980 IEEE International Solid-State Circuits Conference, pp. 150, 151.
Kamuro et al., "A 256K ROM Fabricated Using n-Well CMOS Process Technology", IEEE J. of Solid-State Circuits, SC-17, No. 4, pp. 3-5, Aug. 1982.

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