Writing speed in multi-port static rams

Details Writing speed in multi-port static rams Writing speed in multi-port static rams

1986-02-07

1988-08-16

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, 365203, G11C 700

Patent

active

047648996

ABSTRACT:
A write-bias gate in the form of an FET is provided for each of the bit-lines. Each FET has its drain electrode connected to logic 1 and its source electrode connected to the bit-line. When one port is writing, the write-bias gates on the other port(s) are driven by a signal which causes them to enter a pass condition, supplying extra current to pull up the bit lines of the non-writing port(s).

REFERENCES:
patent: 4499559 (1985-02-01), Kurafuji
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4578780 (1986-03-01), Baba
patent: 4580245 (1986-04-01), Ziegler et al.
patent: 4623990 (1986-11-01), Allen et al.
patent: 4636983 (1987-01-01), Young et al.
patent: 4644500 (1987-02-01), Yonezu et al.
Kendall W. Pope-"Asynchronous Dual Port RAM Simplifies Multiprocessor Systems", Electronic Design News, Sep. 1, 1983.

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