Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2006-05-23
2006-05-23
Mai, Son (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189040
Reexamination Certificate
active
07050337
ABSTRACT:
A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.
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Iwase Yasuaki
Iwata Hiroshi
Morikawa Yoshinao
Nawaki Masaru
Shibata Akihide
Birch & Stewart Kolasch & Birch, LLP
Mai Son
Sharp Kabushiki Kaisha
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