Write recovery time minimization for Bi-CMOS SRAM

Details Write recovery time minimization for Bi-CMOS SRAM Write recovery time minimization for Bi-CMOS SRAM

1993-01-08

1996-04-16

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

36518401, 365204, G11C 700

Patent

active

055089640

ABSTRACT:
A circuit and method for minimizing write recovery time in a Bi-CMOS SRAM by equalizing the bit-line voltages during a read access. A P-channel device whose drain, source and gate are connected to bit, bit-bar, and the write control signal, respectively, indirectly equalizes the bit-lines by equalizing the base voltages of the NPN bit-line load devices only when the column is selected for read access. This technique takes advantage of the current gain of the NPN transistor from the base to the emitter to provide fast bit-line equalization immediately following writes, thus minimizing the write recovery time.

REFERENCES:
patent: 4236229 (1980-11-01), Caudel
patent: 4656608 (1987-04-01), Aoyama
patent: 4866673 (1989-09-01), Tran
patent: 4926383 (1990-05-01), Kertis et al.
patent: 4928268 (1990-05-01), Nogle et al.
patent: 4939693 (1990-07-01), Tran
patent: 4975877 (1990-12-01), Bell
patent: 5075891 (1991-12-01), Yano et al.
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5155703 (1992-10-01), Nogle

Affiliated with

Also associated with

Rating

Write recovery time minimization for Bi-CMOS SRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Write recovery time minimization for Bi-CMOS SRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Write recovery time minimization for Bi-CMOS SRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-330753