Write per bit with write mask information carried on the data pa

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

36518903, 36518901, 3652257, 36523003, G11C 700

Patent

active

055110258

ABSTRACT:
A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.

REFERENCES:
patent: 4817058 (1989-03-01), Pinkham
patent: 4933900 (1990-06-01), Yamaguchi et al.
patent: 5195056 (1993-03-01), Pinkham et al.
patent: 5321651 (1994-06-01), Monk
patent: 5323346 (1994-06-01), Takahashi

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