Write margin of SRAM cells improved by controlling power...

Details Write margin of SRAM cells improved by controlling power... Write margin of SRAM cells improved by controlling power...

2006-01-30

2008-11-04

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000, C365S229000

Reexamination Certificate

active

07447058

ABSTRACT:
Each memory cell has a pair of inverters whose inputs and outputs are connected to each other and holds complementary data respectively in storage nodes which are outputs of the inverters. In a write operation during which the complementary data are written to the storage nodes respectively, the power control circuit sets a power supply voltage of the inverter having the storage node to which low level is written lower than a power supply voltage of the inverter having the storage node to which high level is written. Since power supply capability to the inverter having the storage node to which the low level is written lowers, the voltage of the storage node easily changes to the low level. That is, a write margin of a memory cell can be improved.

REFERENCES:
patent: 6804153 (2004-10-01), Yoshizawa et al.
patent: 7092280 (2006-08-01), Joshi
patent: 58-211391 (1983-12-01), None
patent: 09-051042 (1997-02-01), None

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