Write margin improvement for SRAM cells with SiGe stressors

Details Write margin improvement for SRAM cells with SiGe stressors Write margin improvement for SRAM cells with SiGe stressors

2006-04-10

2008-11-11

Lee, Hsien Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S199000, C257SE27098

Reexamination Certificate

active

07449753

ABSTRACT:
A semiconductor structure including SRAM cells with improved write margins and a method for forming the same are provided. The semiconductor structure comprises a substrate including a core circuit and an SRAM cell. The SRAM cell includes a pull-up PMOS device that comprises a first source/drain region in the substrate, a first SiGe stressor having a portion overlapping at least a portion of the first source/drain region, and a first current-tuning region having a portion overlapping at least a portion of the first source/drain region. The core circuit comprises a core PMOS device that comprises a second source/drain region in the substrate, and a second SiGe stressor having a portion overlapping at least a portion of the second source/drain region. The core PMOS device is free of current-tuning regions.

REFERENCES:
patent: 2005/0112817 (2005-05-01), Cheng et al.
patent: 2005/0218455 (2005-10-01), Maeda et al.

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