Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2006-10-31
2006-10-31
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C029S603100, C029S603150, C029S603160, C216S022000, C216S057000, C360S313000, C360S324000, C438S692000, C438S697000, C438S700000
Reexamination Certificate
active
07129177
ABSTRACT:
During fabrication of a write head via holes are first opened in a gap layer, followed by formation of seed layers instead of the other way around. Moreover a first seed layer is formed, and without the first seed layer being used a second seed layer is formed. The second seed layer (which is the topmost layer) is used in plating to form coils (e.g. of copper) for the write head. After coil formation, the first seed layer is used for plating to form vias (e.g. of NiFe). The two seed layers may be formed in a single operation by using two different targets in a vacuum deposition chamber. Moreover, a single insulation layer is sufficient to insulate and protect all plated elements, regardless of whether they are formed by use of the first seed layer or the second seed layer.
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Colonia Jorge D.
Tsang Douglas Kei Tak
Winton Yvette Chung Nga
Yang Michael Ming Hsiang
Angadi Maki
Hitachi Global Storage Technologies - Netherlands B.V.
Norton Nadine G.
Silicon Valley Patent & Group LLP
Suryadevara Omkar
LandOfFree
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