Write controlled address buffer

Details Write controlled address buffer Write controlled address buffer

1995-08-31

1997-05-13

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 3652335, G11C 700

Patent

active

056298960

ABSTRACT:
An input buffer, for an asynchronous integrated memory circuit incorporating a memory circuit, including a latch circuit controlled by a write enable signal is disclosed. The input stage of the input buffer is connected to a pass gate, which is controlled by the write enable signal so that the pass gate is nonconductive when the write enable signal is active. The output of the pass gate is connected to an input of the latch circuit. The latch circuit is controlled by the write enable signal so that the signal present on the input of the latch is latched when the write enable signal is active. From an output of the latch circuit are obtained true and complementary signals, which are applied to outputs of the buffer circuit. As a result, when the write enable signal is active, the signal present on the input of the buffer is latched and presented to the outputs of the buffer, and the latch circuit is isolated from the input of the buffer until the write cycle is terminated.

REFERENCES:
patent: 5124584 (1992-06-01), McClure
patent: 5469385 (1995-11-01), Smith et al.

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