Write control circuit for semiconductor memory

Details Write control circuit for semiconductor memory Write control circuit for semiconductor memory

1997-07-31

1998-10-20

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518908, 365203, 36523006, 3652335, G11C 700, G11C 800

Patent

active

058256938

ABSTRACT:
A write control circuit for a semiconductor memory that performs a high speed operations determines a write timing of data based on a control signal in cooperation with the logical combination of a write control signal and an equalization signal. The write control circuit further stably performs the write operation. The write control circuit includes a detection signal addition unit that sums output signals from address input buffer units to output a predetermined width pulse signal, an equalization signal generator that receives an output signal from the detection signal addition unit and generates an equalization signal, a write gate controller that logically combines a write control signal from a control signal input buffer and an equalization signal from the equalization signal generator to output a write gate control signal and a data driving control signal, a write data driving unit that outputs data received from a data input buffer based on a data driving control signal from the write gate controller, and a write gate unit that transmits the data output from the write data driving unit to data lines of the memory based on the write gate control signal.

REFERENCES:
patent: 5258951 (1993-11-01), Yu et al.
patent: 5268863 (1993-12-01), Bader et al.

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