Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1986-09-17
1988-05-24
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365233, G11C 1140
Patent
active
047470798
ABSTRACT:
A write circuit for an EPROM device of a microcomputer comprises a first circuit responsive to an external clock signal WCLK and machine clock signals for supplying a clock signal CLK to a program counter of the microcomputer so as to successively increment an address produced in the program counter, where the external clock signal WCLK has a frequency lower than those of the machine clock signals and the clock signal CLK has different frequencies during normal and write-in operation modes so that the address produced in the program counter is successively incremented in synchronism with the machine clock signals during the normal operation mode and is successively incremented in synchronism with the external clock signal WCLK during the write operation mode, and a second circuit responsive to the machine clock signals and a bit data of a LSB of the address from the program counter for generating a bit line clock signal BCLK for inhibiting a write-in data from being written into the EPROM device during a time period in which the address changes.
REFERENCES:
patent: 4707811 (1987-11-01), Takemae et al.
Fears Terrell W.
Fujitsu Limited
LandOfFree
Write circuit for an erasable programmable read only memory devi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Write circuit for an erasable programmable read only memory devi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Write circuit for an erasable programmable read only memory devi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1062923