Word line resistance reduction method and design for high densit

Details Word line resistance reduction method and design for high densit Word line resistance reduction method and design for high densit

1998-05-27

1999-08-03

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438622, H01L 218242, H01L 214763

Patent

active

059337257

ABSTRACT:
A method and design for stitching polysilicon wordlines to straps formed of interconnected metal line segments formed in two or more metallization levels. Each strap comprises a continuous conductive metal line passing alternatively from one metal layer to another in a selected sequence. The sequence of segments in each strap alternates in phase with the sequence in next nearest neighbor straps but may be in phase with second nearest neighbor straps. Thereby the pitch of strap segments on each metallization level is at least twice that of the subjacent polysilicon wordlines. The total length of each metal in each strap is the same in all straps. This arrangement allows the use of metals having different resistivities in each strap with all the straps having identical overall resistance. The metals used in the two or more levels may also have different minimum design rules without compromising the identical overall performance of all the straps. In a second embodiment a method and design is described for doubling the length of polysilicon sub-wordlines in a sub-wordline memory array without reducing performance by connecting sub-wordline to sub-wordline decoders by metal straps connected to the sub-wordlines midpoints.

REFERENCES:
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patent: 5541130 (1996-07-01), Ogura et al.
patent: 5631183 (1997-05-01), Kim et al.
patent: 5644526 (1997-07-01), Mazzali
Saeki et al. "Yield Enhancement Effects of Boosted Dual Word-Line (BDWL) Scheme for High Density DRAMs" IEEE Transactions on Semiconductor Manufacturing, vol. 9, No. 1, Feb. 1996, p. 136ff.

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