Word line drive circuit

Details Word line drive circuit Word line drive circuit

1986-09-22

1988-11-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365226, 365203, 365230, G11C 1300

Patent

active

047886641

ABSTRACT:
In a word line drive circuit providing a word line drive signal for a random access memory, the drive signal has a smooth rising curve to attain a high data reading speed. The circuit comprises two FETs which are series connected between a terminal at which an internally boosted voltage is provided and the ground. The drive signal is provided from the junction of the two FETs. A voltage of the control signal is increased by a boosting capacitor to a level sufficient to keep the FET (connected to the boosted voltage terminal) nonconductive until production of the drive signal is desired. The resultant drive signal has an inverse phase to the phase of the control signals.

REFERENCES:
Ishihara et al., (no title), 1985. 2.11 Nikkei Electronics 243 (1985).
Chan et al.,; "A 100 ns 5V only 64K.times.1 MOS Dynamic RAM"; IEEE Journal of Solid State Circuits; vol. SC-15, No. 5; Oct., 1980; pp. 839-846.
Tamguchi et al.; "Fully Boosted 64K Dynamic RAM With Automatic and Self-Refresh"; IEEE Journal of Solid State Circuits; vol. SC-16, No. 5; Oct., 1981; pp. 492-498.
"Translation of An Official Action"; German Patent Office; May 7, 1987; German patent Application No. P 36 35 344.2.

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