Word driver and decode design methodology in MRAM circuit

Details Word driver and decode design methodology in MRAM circuit Word driver and decode design methodology in MRAM circuit

2006-09-11

2008-12-23

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S046000, C365S055000, C365S074000, C365S097000, C365S173000

Reexamination Certificate

active

07468906

ABSTRACT:
A word line driver and decoder for use in a magnetic memory includes a main word line driver and a sub word line driver that cooperate to drive current on a selected one from a number of the magnetic memory's word lines. The main word line driver and sub word line driver employ pull up and pull down transistors that configured to drive current on the selected word line in either a read or write ‘0’ direction or a read or write ‘1’ direction in response to control signals that allow reliable magnetic memory operation. An address decoder selects and activates a multiplexer in the sub word line driver to coordinate the current drive. The main word line driver employs current mirrors, transistor switches, and logic control to prevent direct Vdd to Vss shorting in transitioning from ‘0’ and ‘1’, and read and write data storage operations.

REFERENCES:
patent: 6055178 (2000-04-01), Naji
patent: 6256224 (2001-07-01), Perner et al.
patent: 6335890 (2002-01-01), Reohr et al.
patent: 2005/0117426 (2005-06-01), Theel

Affiliated with

Also associated with

Rating

Word driver and decode design methodology in MRAM circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Word driver and decode design methodology in MRAM circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Word driver and decode design methodology in MRAM circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4038013