Wiring structure to minimize stress induced void formation

Details Wiring structure to minimize stress induced void formation Wiring structure to minimize stress induced void formation

2007-11-27

2007-11-27

Baumeister, B. William (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S048000, C257SE29112, C438S622000, C438S637000, C438S468000, C438S018000

Reexamination Certificate

active

10899252

ABSTRACT:
A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n” overlapping segments and at least one bending portion. The other end of the protrusion is connected to the bottom of a via which has an overlying second conducting layer. A bend is formed by overlapping the ends of two adjacent segments at an angle between 45° and 135°. The protrusion may also include at least one extension at a segment end beyond a bend. A bending portion and extension are used as bottlenecks to delay the diffusion of a vacancy from the large area portion to the vicinity of the via and is especially effective for copper interconnects or in a via test structure.

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