Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-27
2004-03-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06708318
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a wiring resistance correcting method, and more particularly to a designing method which corrects algorism-wisely an error between a resistance value on a mask CAD and a resistance value on a real chip in simulation processing at the occasion of designing a semiconductor integrated circuit, thereby increasing the accuracy in timing analysis and voltage drop analysis so as to improve the yield without causing malfunction due to undervoltage.
2. Description of the Related Art
In a conventional semiconductor designing method, circuit designing and layout designing are carried out on a computer to create mask information, and mask processing is carried out by using the data, thereby manufacturing a semiconductor device.
Where the semiconductor device is actually manufactured, the following process is adopted. First, a capacitance and resistance value of a wiring are taken out from the mask information data after layout designing considering a wiring length, wiring width and wiring distance. Simulation of delay computing and voltage drop is carried out using the data thus taken out. The simulation result is fed back to take measures before the mask processing. The technique for increasing the yield by taking the measures before the mask processing has been well known.
In this designing flow, as seen from
FIG. 10
, each wiring resistance information
102
is taken out from a layout data
101
and the value is used, as it is, as an input with no correction to voltage drop analysis processing
103
. Assuming that the film is constant within the same wiring and the wiring layer is located on a horizontal plane with no warp, with a wiring resistance being given to each wiring layer with a parameter of a sheet resistance, the layout data
101
on the conventional mask CAD is generally acquired by a two-dimensional function of a wiring length and a wiring width.
However, in the manufacturing process for the semiconductor device, the wiring shape on the mask data and that on a real chip are different due to the material, width, distance, arrangement state of the wiring/insulating film. As a countermeasure for the error due to light diffraction among the errors between the mask data and the real data, an OPC (Optical Proximity Correction) technique is generally known. As a countermeasure for occurrence of a change in the film thickness, various flattening techniques have been adopted. There is also a problem in the flattening processing. Particularly, a CMP (Chemical/Mechanical Polishing) technique presents problems of scraping of a wiring layer and reduction in a film. As a countermeasure for this, as disclosed in JP-A-2000-3912, there has been proposed a technique for controlling an etching speed and preventing scraping of the wiring layer in a manner of coating an upper layer of the wiring layer with a film having a low etching speed.
As regards the voltage drop analysis technique, processing for analyzing whether or not the voltage satisfies an operable voltage range (e.g. JP-A-9-55433) has been generally adopted.
However, there is a problem that it difficult to manufacture a device with a shape with complete coincidence by the processing of approximating the mask data and the shape on the real chip according to a conventional technique. Where the wiring width is large, it is also difficult to suppress the scraping of the wiring layer by the method of fixing the scraping of the wiring layer and insulating film layer in the CMP technique. Where there: are changes in the thickness of the wiring layer and insulating film layer, as the size of the multi-layer wiring structure increases, a warp occurs in the wiring of the upper layer according to the wiring shape of the lower layer. It is further difficult to suppress the warp. Where there is a change in the wiring film thickness or a warp of the wiring on the actual mask data, if the voltage drop is acquired on the basis of the two-dimensional data on the mask CAD tool as in the prior art, the capacitance and resistance on the tool are different from those of the actual chip. Likewise, the voltage drop differs between the result by simulation and that on the real chip. In this case, although the LSI has been operated at the time of simulating, the corresponding actual chip malfunctions, thereby decreasing the production yield.
SUMMARY OF THE INVENTION
This invention has been accomplished in view of the above circumstance, and intends to provide a designing technique which computes a change between the resistance on a real chip and that in simulation, thereby making it possible to detect the problem on the real chip with the aid of the simulation.
In order to attain the above object, in a method of designing a semiconductor integrated circuit having a wiring on the surface of a semiconductor substrate, a wiring resistance correcting method according to this invention is characterized by comprising: a wiring resistance correcting step of correcting a resistance of the wiring according to film thickness information.
In the second aspect of this invention, the semiconductor substrate is a silicon wafer, and the wiring is a metallic wiring for connecting terminals of transistors arranged on the silicon wafer, the wiring resistance correcting step correcting the resistance of the metallic wiring according to the film thickness information.
The third aspect of this invention is characterized in that the wiring resistance correcting step comprises the steps of:
acquiring a varying function by computing a variation from a designed value of the wiring film thickness in manufacturing an LSI;
computing a wiring film thickness on a real chip formed from the semiconductor substrate on the basis of the varying function; and
correcting a layout data which is designed value information of the wiring film thickness on the basis of a difference between the designed value of the wiring film thickness and its value on the real chip.
The fourth aspect of this invention is characterized in that the wiring resistance correcting step comprises the steps of:
computing a wiring width so that the resistance of the wiring becomes a specified resistance, and
changing a layout data to provide the wiring width thus computed.
The fifth aspect of this invention is characterized in that the wiring resistance correcting step comprises the steps:
computing a change in a wiring length of an upper layer on the basis of a stacking state of a lower layer in a multiplayer wiring for forming an LSI by stacking a wiring layer and an insulating film layer, and
correcting the resistance into a resistance corresponding to the wiring length thus computed.
In such a configuration, the data of the resistance outputted from the mask CAD tool can be corrected to a value more approximate to the resistance when the LSI is actually manufactured, simulation such as delayed value analysis, voltage drop analysis, etc. can be effected with great accuracy.
Specifically, for example, the data of the resistance outputted from the mask CAD tool is corrected considering a change in the resistance when the LSI is manufactured. Where it is difficult to create previously the information for considering a change in the resistance when the LSI is manufactured, the above information is produced through automatic computation.
The mask CAD tool accesses the same data base with the one which is accessed by a tool for simulation. In order to deal with the case where it is difficult to correct the actual resistance of each wiring, parameters in the data base is modified to change the virtual wirings and layout in accordance with the corrected resistance.
Further, in order to consider the warp of the wiring on the upper layer due to changes in the wiring shape in the lower layer, the wiring length of the upper layer is computed on the basis of the stacking state of the lower layer.
REFERENCES:
patent: 6100177 (2000-08-01), Noguchi
patent: 6182269 (2001-01-01), Laubhan
patent: 6185722 (2001-02-01), Darden et al.
patent: 6219631 (2001
Kimura Fumihiro
Satoh Kazuhiro
Lin Sun James
Smith Matthew
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