Wiring layers for a semiconductor integrated circuit device

Details Wiring layers for a semiconductor integrated circuit device Wiring layers for a semiconductor integrated circuit device

1998-08-04

2000-05-16

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257368, 257367, 257296, 257297, 257302, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

060640979

ABSTRACT:
A semiconductor integrated circuit device has macrocells composed of CMOS transistors. In a first wiring layer of the macrocells, a power source line coupled to the sources of P-channel MOS transistors and a ground line coupled to the sources of N-channel MOS tranistors are formed so as to extend in a first direction. In a second wiring layer of the macrocells, a power supply line connected to the power source line, a ground voltage supply line connected to the ground line, a first bias line for feeding a bias to the N well for the P-channel MOS transistors, and a second bias line for feeding a bias to a semiconductor substrate are formed recurrently so as to extend-in a second direction perpendicular to the first direction.

REFERENCES:
patent: 4884118 (1989-11-01), Hui et al.
patent: 4959704 (1990-09-01), Isomura et al.
patent: 4982114 (1991-01-01), Nakamura et al.

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