Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-15
2004-06-01
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06745378
ABSTRACT:
CROSS-REFERENCE TO RELATED APLICATIONS
This application is based upon and claims priority of Japanese Patent Applications No. 2001-269205, filed in Sep. 5, 2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring designing method for a semiconductor integrated circuit and, more particularly, to a structure of an intersection portion of stripe wiring, each of which is composed of a plurality of strands limited to a fixed width or lower, and a method of designing the same.
2. Description of the Prior Art
In recent years, with promotion of much higher integration of a semiconductor integrated circuit, a copper wiring has replaced an aluminum wiring that had mainly been used. The copper wiring has advantages of a lower value of resistance, and higher resistance to electromigration compared with an aluminum wiring having an equal width, and thus it is suitable for forming a micro-wiring.
The copper wiring is generally formed by a method called a damascene method (or dual damascene method). According to the damascene method, the copper wiring is formed in such a manner that a trench is formed in an insulating film on a semiconductor substrate, and copper is embedded in the trench by use of a method such as plating, followed by removing a portion of the copper on the insulating film by a chemical mechanical polishing (CMP) method, while leaving a portion of the copper in the trench.
The inventors of this application consider that there are the following problems in a conventional wiring designing method. That is, mounting narrow and wide wirings mixedly on the same substrate makes it difficult to perform uniform polishing by the CMP method. For example, if CMP polishing is performed according to the wide wiring, the narrow wiring becomes thin.
To solve such a problem, a limitation must be placed on a width of wiring, and widths of all wirings must be set equal to a limit value (referred to as maximum line width, hereinafter) or lower. For a similar reason, an occupancy rate of a wiring per unit area must be set so as not to exceed a maximum occupancy rate of a wiring decided by constraints imposed on a manufacturing process. Specifically, in the case of a wiring arrangement, through which a large current flows, as shown in
FIG. 1
, the wiring is divided into a plurality of wirings narrower than the maximum line width, and a space between the wirings is set so as not to exceed the maximum occupancy rate of a wiring. Hereinafter, the plurality of wirings connected in parallel as shown in
FIG. 1
are called strands, and a collection of these strands is called a stripe wiring.
For example, in an intersection (connection) portion of two stripe wirings, simple intersection of the two stripe wirings results in a state like that shown in
FIG. 2
, where a maximum occupancy rate of a wiring per unit area is exceeded in the intersection portion of the two stripe wirings A and B. Conventionally, therefore, any one of the following methods has been employed: thinning strands in the intersection portion so as not to exceed the maximum occupancy rate of a wiring, shown in
FIG. 3
; and formation of a connecting wiring
53
in the other wiring layer, and electrical connection of strands
51
and
52
of the stripe wirings A and B with each other through a wiring
53
and a contact hole
54
, shown in FIG.
4
.
However, thinning the strands in the intersection portion shown in
FIG. 3
may cause excessive supplying of current to partial strands, or limit the amount of current to be supplied to the stripe wirings, making it impossible to supply a necessary amount of current. In the case of the formation of the connecting wiring
53
in the other wiring layer shown in
FIG. 4
, no limitations are imposed on the amount of current, but the use of the other wiring layer reduces a degree of freedom for wiring designing.
SUMMARY OF THE INVENTION
Objects of the present invention are to provide a wiring structure and a wiring designing method capable of providing a high degree of freedom of wiring designing, setting an occupancy rate of a wiring per unit area in an intersection portion of two stripe wiring equal to/lower than a maximum occupancy rate of a wiring, and supplying a necessary amount of current.
In accordance with an aspect of the invention, a wiring designing method of the present invention is provided for designing an intersection portion of stripe wirings composed of a plurality of strands limited to a fixed width or lower. This method comprises the steps of: setting first and second stripe wirings composed of a plurality of strands limited to a fixed width or lower to virtually intersect each other; setting a strand belonging to any one of the first and second stripe wiring among the strands in the intersection portion of the first and second stripe wirings to be changed for position; deciding a reference position; and moving the strand to be changed for position in a direction away from the reference position to a position where an occupancy rate of a wiring for each of the first and second stripe wirings in the intersection portion becomes equal to/lower than at least a maximum occupancy rate of a wiring decided by constraints imposed on a manufacturing process.
In accordance with another aspect of the invention, a wiring designing method of the present invention is provided for designing an intersection portion of stripe wirings composed of a plurality of strands limited to a fixed width or lower. This method comprises the steps of: setting first and second stripe wirings to virtually intersect each other; forming L-shaped strands by connecting strands of one having a smaller number of strands, of the first and second stripe wirings, sequentially from an outer strand with strands of the other stripe wiring; forming auxiliary strands from corners of the L-shaped strands in a direction perpendicular to center lines of the first and second stripe wirings; deciding a reference position; and moving the auxiliary strands in a position away from the reference position to positions where an occupancy rate of a wiring for each becomes equal to/smaller than a maximum occupancy rate of a wiring decided by constraints imposed on a manufacturing process.
In accordance with yet another aspect of the invention, a semiconductor device of the present invention is provided, comprising: a first stripe wiring composed of a plurality of strands limited to a fixed width or lower; and a second stripe wiring composed of a plurality of strands limited to a fixed width or lower, and having an intersection portion with the first stripe wiring. In this case, a space between those among strands in the intersection portion, belonging to one of the first and second stripe wiring, is set wider than a space between strands in a portion other than intersection portion, belonging to the same stripe wiring.
According to the semiconductor device of the present invention, the first and second stripe wirings are set to virtually intersect each other, positions of the strands in the intersection portion between the first and second stripe wirings are shifted in a manner that an occupancy rate of a wiring per unit area becomes equal to/lower than a maximum occupancy rate of a wiring, and strands are formed in the intersection portion and its vicinity according to a predetermined reference.
Thus, according to the present invention, since the first and second stripe wirings are connected with each other in one wiring layer without using any other wiring layers, a degree of freedom of wiring designing is increased. Moreover, according to the present invention, since no thinning is carried out for the strands in the intersection portion between the stripe wiring, it is possible to prevent excessive supply of current to partial strands and a limitation placed on the amount of current to be supplied to the stripe wiring, thus a necessary amount of current can be supplied. As a result, it is possible to secure wiring reliability.
REFER
Westerman Hattori Daniels & Adrian LLP
Whitmore Stacy A.
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