Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-07-19
2004-06-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189040, C365S193000, C365S194000, C365S230030, C365S230060, C365S230080, C365S233100
Reexamination Certificate
active
06744685
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device which stores data by storing an electric charge, a method for refreshing the semiconductor device, and electronic equipment equipped with the semiconductor device.
DESCRIPTION OF RELATED ART
A VSRAM (Virtually Static RAM) is one type of semiconductor memory. Although memory cells of the VSRAM are the same as memory cells of a DRAM, the VSRAM does not need multiplexing of the column address and the row address. Moreover, the VSRAM can be used without taking refreshing into consideration. Specifically, the VSRAM is provided with transparency of refreshing.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device including a memory cell array, in which memory cells for which refreshing is needed are arranged in an array, a method for refreshing the semiconductor device, and electronic equipment equipped with the semiconductor device.
One aspect of the present invention provides a method for refreshing a semiconductor device including a memory cell array, in which memory cells for which refreshing is needed are arranged in an array,
wherein the memory cell array is divided into a plurality of blocks, and
wherein data read or write in one block among the plurality of blocks and refreshing in at least one of the other blocks among the plurality of blocks are performed concurrently,
wherein an address signal from outside is input to the semiconductor device,
wherein the address signal comprise a block address signal for selecting the one block, and
wherein the block address signal is a signal of a lower-order bit of the address signal including a least significant bit.
The term “two events are performed concurrently” used in this specification means that at least part of the events overlaps each other in time during the execution of the events.
Another aspect of the present invention provides a semiconductor device including a memory cell array, in which memory cells for which refreshing is needed are arranged in an array,
wherein the memory cell array is divided into a plurality of blocks, and
wherein the semiconductor device includes a control section which controls data read or write in one block among the plurality of blocks and refreshing in at least one of the other blocks among the plurality of blocks to be performed concurrently,
wherein an address signal from outside is input to the semiconductor device,
wherein the address signal comprise a block address signal for selecting the one block, and
wherein the block address signal is a signal of a lower-order bit of the address signal including a least significant bit.
Still another aspect of the present invention provides a semiconductor device comprising:
a memory cell array divided into a plurality of blocks, each of the plurality of blocks including memory cells;
a control section which controls data read or write in one block among the plurality of blocks and refreshing in at least one of the other blocks among the plurality of blocks to be performed concurrently; and
an address buffer section to which an external access signal including a block address signal is input,
wherein the block address signal is used to select the one block in which the data read or write is performed, and
wherein the block address signal is a signal of a lower-order bit of the address signal including a least significant bit.
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Nelms David
Oliff & Berridg,e PLC
Pham Ly Duy
Seiko Epson Corporation
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