Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-19
2003-01-21
Teska, Kevin J. (Department: 2123)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S087000, C716S030000, C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
06510544
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to wiring design apparatus and a method thereof for designing an optimum route of wiring between bonding pads disposed on a semiconductor chip and pins (terminals) disposed in a semiconductor package.
BACKGROUND OF THE INVENTION
PUPA 5-143689 and others disclose wiring design apparatus for automatically or semi-automatically designing wiring of a printed circuit substrate used in electronic equipment for wiring between bonding pads disposed on a semiconductor chip and pins (terminals) disposed on a semiconductor package.
With such prior art technology, wiring of a semiconductor package can be automatically or semi-automatically done according to a design rule indicating the upper limits of a space between pins and the width of the wire occupying the space between the pins.
However, the wiring design of such prior art technology may result in a local concentration of wiring due to a condition of disposition of parts and the positional relationship of pins. The local concentration of wiring may cause deterioration of the electrical characteristic of a product and has to be eliminated.
In order to eliminate such concentration of wiring, a manual correction of the wiring and change of disposition of parts have been so far employed.
This invention is conceived in view of the above described problems of the prior art technology and aims at providing a wiring design apparatus and a method thereof for automatically designing wiring which conforms to a design rule and does not involve a local concentration of wiring without requiring a manual correction of wiring and disposition of parts.
It is another object of this invention to provide a wiring design apparatus and a method thereof which allows wiring to be designed according to a design rule without depending on net information of the disposition of parts and the positional relationship of pins interconnected and with a local concentration of wiring suppressed.
BRIEF SUMMARY OF THE INVENTION
In order to achieve the above objectives, this invention provides a wiring design apparatus for designing wiring which provides connections among a plurality of terminal points provided on one plane in a route passing an area on said plane other than an area where wiring is prohibited, comprising; monitoring side generating means for generating a virtual side for monitoring wiring density (monitoring side) between any two of said terminal points and wiring prohibiting areas (element) on said plane, and wiring design means for designing routes of wiring (wiring routes) connecting said terminal points based on the width of wiring crossing each of said monitoring side.
Preferably, said wiring design means generates wiring route according to a design rule at least indicating the space of said elements, the proportion of the width of said wiring occupying the space between said elements (wiring density), the space between wires of said wiring, and the width of said wiring.
Preferably, said wiring design means further comprises; candidate route generating means for successively searching the routes of said wiring according to said design rule for each of portions of each route which is divided into one or more portions (partial routes) from a terminal point where said wiring starts to a terminal point where it terminates to generate one or more candidates of said partial route (candidate routes), route length evaluating means for calculating the value of a route length evaluation of each of said candidate routes based on the length of said candidate routes generated and the wiring density of the monitoring side crossing said candidate route, said value of route length evaluation assuming a larger value when the length of said candidate route is longer and when the width of wiring crossing said monitoring side which is crossed by said candidate route is wider, route selecting means for selecting a candidate route having the minimum value of said calculated route length evaluation as said partial route among said generated candidate routes, and partial route connecting means for connecting said selected partial route to design the route of each of said wiring.
Preferably, said route length evaluating means calculates said value of route length evaluation by multiplying the route length of each of said candidate routes by a weighting coefficient which assumes a larger value when the wiring density of said monitoring side crossing each of said generated candidate routes is larger.
Preferably, said candidate route generating means generates said candidate route while allowing it to cross other wiring routes, said route length evaluating means calculates the value of the route length evaluation of said candidate route generated with crossing allowed, and said route selecting means changes another wiring route crossing said selected partial route with said partial route which is so selected as to eliminate crossing.
The wiring design apparatus of this invention designs wiring which connects between bonding pads of a semiconductor chip and pins (terminals) of a semiconductor package in a route passing wiring plane of the semiconductor package while avoiding wiring prohibiting area of the semiconductor package, conforming to the design rule and suppressing a local concentration of wiring.
A connection between bonding pads of a semiconductor chip and pins (terminals) of a semiconductor package is now described hereunder as an example.
The monitoring side generating means generates a virtual side (monitoring side) used for determining whether or not a concentration of wiring occurs in a portion where it is empirically assumed that wiring tends to concentrate, such as a space between neighboring terminal pins disposed in a corner of a pin grid array, or a space between neighboring pins and a prohibiting area in the wiring plane of a semiconductor package.
The wiring designing means extends partial routes successively from a bonding pad based on design information indicating the relationship of connection between a pin of a semiconductor package and a bonding pad of a semiconductor chip, and wiring density in the space (the width of wiring occupying the space) between pins, prohibiting areas, or a pin and a prohibiting area (a pin and a prohibiting area are collectively referred to as an element).
Further, the wiring designing means successively selects a partial route so as to relax the wiring density on the monitoring side to design a wiring route between pins and bonding pads.
In the wiring designing means, the candidate route designing means generates one or more candidate(s) of a route which can connect from a node to a next node starting at the beginning point of wiring toward a terminating point while allowing crossing with another wiring according to a design rule and using a search algorithm such as Dijkstra method, for example.
Specifically, the candidate route designing means generates as many routes as possible successively connecting from a bonding pad to a first node, from a node to a next node, or from a node to a pin and provides them as candidate routes.
The route length evaluating means provides the length of a candidate route as a value of the route length evaluation when the candidate route does not cross a monitoring side while it provides the length of a candidate route multiplied by a coefficient as a candidate route when the candidate route crosses the monitoring side, the coefficient depending on the wiring density (on the monitoring side) of wiring which has been so far drawn so as to trace a route crossing the monitoring side.
For example, the route length evaluating means calculates a value of the route length evaluation which assumes a larger value when the candidate route is longer and the wiring density of monitoring sides crossing a candidate route is larger, for example, by using a coefficient of “1” when a candidate route crosses a monitoring side which is not crossed by any other wiring and a coefficient of “10” when a candidate route crosses a monitoring side having wiring density n
Hirayama Kazuhiko
Katsumata Minoru
Matsumoto Hiroyuki
Blecker Ira D.
Ferris Fred
Teska Kevin J.
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