Wirebondless wafer level package with plated bumps and...

Details Wirebondless wafer level package with plated bumps and... Wirebondless wafer level package with plated bumps and...

2011-06-21

2011-06-21

Nguyen, Thanh (Department: 2893)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S106000, C438S118000, C438S612000, C438S613000, C438S617000, C257SE21002, C257SE23021

Reexamination Certificate

active

07964450

ABSTRACT:
A semiconductor package includes a carrier strip having a die cavity and a plurality of bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip using a die attach adhesive. In one embodiment, a top surface of the semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. Underfill material is deposited into the die cavity between the semiconductor die and a surface of the die cavity. In one embodiment, a passivation layer is deposited over the semiconductor die, and a portion of the passivation layer is etched to expose a contact pad of the semiconductor die. A metal layer is deposited over the package. The metal layer forms a package bump and a plated interconnect between the package bump and the contact pad of the semiconductor die. Encapsulant is deposited over the semiconductor package.

REFERENCES:
patent: 6191494 (2001-02-01), Ooyama et al.
patent: 7081403 (2006-07-01), Kirloskar et al.
patent: 2005/0158009 (2005-07-01), Eichelberger et al.
patent: 2007/0108605 (2007-05-01), Yoon et al.
patent: 2008/0169548 (2008-07-01), Baek

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