Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1993-11-18
2001-07-24
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S652000, C438S685000, C438S686000
Reexamination Certificate
active
06265300
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computer chip manufacturing. In particular, the invention relates to the design of an improved wire bonding surface and method for wire bonding for use with semiconductor devices using compliant dielectric materials.
2. Prior Art
Conventional Semiconductor devices are formed by the selective deposition of numerous materials including silicon dioxide (SiO
2
) dielectric layers and conductive layers upon silicon wafers. The uppermost conductive layers are typically made of Aluminum. The silicon wafers are then sawed to form individual computer chips. The top of each chip typically includes a number of exposed metal regions, known as bonding pads. The connection to packaging and to external devices is accomplished by bonding leads to these bonding pads. These bonding pads are typically formed of aluminum. Conventional bonding methods include the use of thermosonic or ultrasonic bonding methods. Thermosonic bonding is typically used to bond leads having gold wires while ultrasonic is typically used with leads having aluminum wires.
Polyimides are increasingly being studied for forming inter-layer dielectric layers as well as for final passivation of integrated circuits. Though polyimide layers are easy to process and have good planarization, these layers are highly compliant. When conventional bonding pad structures and automated wire bonding processes are used with semiconductor devices having polyimide dielectric layers, serious reliability problems and yield reductions occur. Poor wire pad strength and unacceptable levels of failures occur over a wide range of machine parameters. These failures are primarily due to the compliant nature of the polyimide which does not allow for efficient coupling of the ultrasonic energy at the interface between the lead and the bonding pad surface. The ultrasonic energy is dissipated within the polyimide layers instead of into the bonding process.
What is needed is a bonding pad structure and a method of bonding for forming a high yield, low failure semiconductor chip for use with compliant dielectric materials, and in particular polyimide. This structure and method should use conventional materials for forming bonding pads and should allow for the use of conventional bonding methods and machinery.
SUMMARY OF THE INVENTION
An improved bonding pad structure and a method for wire bonding is disclosed for use with compliant dielectric material. A rigid layer is formed between the compliant dielectric layer and the bonding pad layer. The rigid layer increases the stiffness of the structure overlying the compliant dielectric layers such that mechanical ultrasonic energy is not dissipated into the dielectric. Thus an effective bond may be achieved which will allow for the use of conventional bonding machinery methods and materials. The invention is described with reference to the use of polyimide dielectric layers, however it would be applicable to the use of any compliant dielectric. The bonding pad structure is achieved by depositing a rigid interposed layer over the compliant dielectric layer. Though any compatible rigid material may be used, the interposed layer is preferably titanium. For example, nickel, copper or molybdenum may also be used. The interposed layer may be deposited after vias have been formed so as to simultaneously form plugs and the interposed layer. The interposed layer may also be deposited after the formation of plugs and the planarization of polyimide and plug surfaces. Next, a layer of aluminum is deposited over the wafer surface to form a bonding pad layer. The bonding pad layer and the interposed layer are then etched to form a bonding pad and an interposed pad. Conventional processing steps are then used to form a passivation layer having openings overlying the bonding pads. Leads are then bonded to the exposed surfaces of the bonding pads.
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Bhansali Ameet S.
Chen Shou H.
Gasparek Michael J.
Jeng Kevin
Lee Ching C.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Picardat Kevin M.
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