Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2002-09-30
2004-03-23
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S784000, C257S780000, C257S778000, C257S779000, C257S790000
Reexamination Certificate
active
06710434
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a window-type semiconductor package for preventing chip-cracking and wire-sweeping, and a method for fabricating the same.
BACKGROUND OF THE INVENTION
Window-type semiconductor packages are advanced packaging technology, characterized by forming at least an opening penetrating through a substrate, allowing a chip to be mounted over the opening, and electrically connected to the substrate by bonding wires through the opening. This arrangement allows length of the bonding wires to be effectively shortened, thereby facilitating electrical transmission or performances between the chip and the substrate.
A conventional window-type semiconductor structure
1
is illustrated in
FIGS. 3A and 3B
, wherein a substrate
10
has an upper surface
100
and a lower surface
101
, and is formed with an opening
102
penetrating through the same. A chip
11
is mounted on the upper surface
100
of the substrate
10
in a face-down manner as to allow bond pads
111
formed on an active surface
110
of the chip
11
to be exposed to the opening
102
. A plurality of bonding wires
12
are formed through the opening
102
and bonded to the exposed bond pads
111
of the chip
11
, so as to electrically connect the active surface
110
of the chip
11
to the lower surface
101
of the substrate
10
. Then, a lower encapsulant
13
is formed on the lower surface
101
of the substrate
10
by a printing process, for encapsulates the bonding wires
12
and sealing the opening
102
.
However, due to material mismatch in coefficient of thermal expansion (CTE) between the lower encapsulant
13
(formed by a resin compound) and the chip
11
directly in contact with the lower encapsulant
13
, under a high temperature condition such as curing of the lower encapsulant
13
or subsequent thermal cycles, the chip
11
particularly at end portions thereof (as circled in
FIG. 3B
) would be subject to greater thermal stress from the lower encapsulant
13
and cracks due to shrinkage of the lower encapsulant
13
, chip-cracking problems are severe for relatively long or large-scale chips, making reliability and yield of fabricated products undesirably degraded. Moreover, during fabrication of the lower encapsulant
13
, the bonding wires
12
directly encounter mold flow impact from the resin compound for forming the lower encapsulant
13
, and thereby easily lead to wire-sweeping or short-circuiting problems.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a window-type semiconductor package and a fabrication method thereof, for enhancing mechanical strength of a chip mounted therein and for preventing chip cracks from occurrence.
Another objective of the invention is to provide a window-type semiconductor package and a fabrication method thereof,
A further objective of the invention is to provide a window-type semiconductor package and a fabrication method thereof,
In accordance with the above and other objectives, the present invention proposes a window-type semiconductor package and a fabrication method thereof. The window-type semiconductor package comprises: a substrate having an upper surface and a lower surface opposed to the upper surface, and formed with at least an opening penetrating through the upper and lower surfaces, at least a chip having an active surface and a non-active surface opposed to the active surface, wherein the active surface of the chip is mounted over the opening on the upper surface of the substrate, allowing a conductive area of the active surface to be exposed to the opening; a plurality of bonding wires formed through the opening for electrically connecting the conductive area of the chip to the lower surface of the substrate; a non-conductive material applied over the conductive area of the chip within the opening of the substrate; an upper encapsulant formed on the upper surface of the substrate for encapsulating the chip; a lower encapsulant formed on the lower surface of the substrate for encapsulating the bonding wires and the non-conductive material; and a plurality of solder balls implanted on the lower surface of the substrate at area outside the lower encapsulant.
The non-conductive material applied over the conductive area of the chip is low in viscosity, and has coefficient of thermal expansion (CTE) between that of the chip and of a resin material for fabricating the lower encapsulant; preferably, the non-conductive material may be silicone. The non-conductive material is applied by printing or dispensing technique through the use of a stencil mounted on the lower surface of the substrate around the opening without interfering the bonding wires, wherein the stencil is formed with a through hole corresponding in position to the conductive area of the chip, so as to allow the non-conductive material to be applied through the through hole of the stencil into the opening of the substrate and over the conductive area of the chip.
The above semiconductor package provides significant benefits. The non-conductive material interposed between the chip and the lower encapsulant, has low viscosity and intermediate CTE, and may serve as buffer to reduce thermal stress exerted from the lower encapsulant to the chip and to prevent the chip from cracking at end portions thereof, which chip-cracking is discussed in the prior art and caused by shrinkage of a lower encapsulant in direct contact with a chip during a curing or subsequently high-temperature process. Moreover, the non-conductive material encapsulates part of the bonding wires within the opening of the substrate; this helps secure the bonding wires in position and prevent wire-sweeping from occurrence during fabrication of the lower encapsulant for encapsulating the bonding wires. Therefore, in free concern of chip-cracking and wire-sweeping, reliability and yield of the semiconductor package can be desirably improved.
REFERENCES:
patent: 6218731 (2001-04-01), Huang et al.
patent: 6265768 (2001-07-01), Su et al.
patent: 6501170 (2002-12-01), Dickey et al.
Fulbright & Jaworski LLC
Talbott David L.
Thai Luan
Ultratera Corporation
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