Whole chip ESD protection

Details Whole chip ESD protection Whole chip ESD protection

2002-07-25

2004-05-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S173000

Reexamination Certificate

active

06730968

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a whole chip electrostatic discharge, ECD, circuit and method.
In particular, this invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths.
2. Description of Related Art
FIG. 1
shows a prior art input/output protection circuit. This protection circuit is placed next to each input/output (I/O) pad. Each protection circuit, like the one shown in
FIG. 1
, is used to protect only one I/O pad. If one of the I/o pads is zapped with high voltage or high current, the electrostatic discharge, ESD, current
170
only flows through the protection circuit adjacent to the zapped I/o pad. The circuit in
FIG. 1
is connected to the supply voltage Vcc
190
and to Vss
150
or ground. The circuit includes a p-channel metal oxide semiconductor field effect transistor PMOS FET device
110
and an n-channel metal oxide semiconductor field effect transistor NMOS FET device
120
. It also includes a bipolar junction transistor
180
and a resistor
160
.
U.S. Pat. No. 6,344,412 (Ichikawa, et al.) “An Integrated ESD protection method and system” describes a method and a system for protecting integrated circuits from electrostatic discharge damage.
U.S. Pat. No. 6,262,873 (Pequignot, et al.) “A Method for Providing ESD Protection for an Integrated Circuit” discloses a method for providing electrostatic protection for integrated circuits.
U.S. Pat. No. 6,218,704 (Brown, et al.) “ESD Protection Structure and Method” discloses an integrated circuit structure and method for electrostatic discharge protection for chips.
BRIEF SUMMARY OF THE INVENTION
It is the objective of this invention to provide a whole chip electrostatic discharge, ECD, circuit and method.
It is further an object of this invention to provide a means of distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths.
The objects of this invention are achieved by a whole chip electrostatic discharge, ECD, first embodiment circuit made up of a PN diode whose p-side connects to the input/output, I/O pad to be protected and whose N-side is connected to Vcc supply voltage, a PMOS FET plus NMOS FET 2-device input stage connected between Vcc and Vss, a resistor plus NMOS FET first mid stage connected between Vcc and Vss (ground). The circuit of the invention also contains a resistor to ground second mid-stage, and a PMOS FET plus NMOS FET output stage connected between Vcc and Vss (ground) whose input connects from the mid stages and whose output drives an unused I/O pad.
The objects of this invention are further achieved by a whole chip electrostatic discharge ECD method comprising the steps of connecting all input/output, I/O pads to each other with double isolation, and inserting a circuit of the first embodiment of this invention between each adjacent I/O pair on a semiconductor chip.


REFERENCES:
patent: 5623156 (1997-04-01), Watt
patent: 6218704 (2001-04-01), Brown et al.
patent: 6262873 (2001-07-01), Pequignot et al.
patent: 6344412 (2002-02-01), Ichikawa et al.
patent: 6583972 (2003-06-01), Verhaege et al.

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