Well structure non-volatile memory device and method for fabrica

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257314, 257316, 257319, 257355, H01L 2976, H01L 29788, H01L 2362

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active

059628880

ABSTRACT:
In a semiconductor memory device, a plurality of first and second impurity regions of a second conductivity type are provided as wells in a semiconductor substrate of a first conductivity type. Outside of the first and second impurity regions, a plurality of third impurity regions of the first conductivity type are provided as wells in the substrate. A plurality of fourth impurity regions of the first conductivity type are provided as wells in the plurality of first impurity regions of the second conductivity type. The first impurity regions of the second conductivity type each have an impurity concentration which gradually decrease with increasing depth below the top surface of the semiconductor substrate, and the fourth impurity regions of the first conductivity type have at least two impurity concentration peaks below the top surface of the semiconductor substrate. A memory cell can be reliably erased by forming a retrograde pocket well for a memory cell array, and a diffusion well surrounding the pocket well, thus maintaining a high breakdown voltage between the pocket well and the substrate.

REFERENCES:
Tomoharu Tanaka et al. "A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution", 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 105-106.
Kang-Deog Suh et al.; "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme" IEEE Journel of Solid-State Circuits, vol. 30, No. 11, Nov. 1995; pp. 1149-1156.
John Yuan-Tai Chen; "Quadruple-Well CMOS for VLSI Technology" IEEE Transactions on Electron Devices, vol. ED-31, No. 7, Jul. 1984; pp. 910-919.

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