Well isolation trenches (WIT) for CMOS devices

Details Well isolation trenches (WIT) for CMOS devices Well isolation trenches (WIT) for CMOS devices

2007-09-11

2007-09-11

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S231000, C438S238000, C438S243000, C438S386000, C438S387000, C438S391000, C257SE21546, C257SE21548, C257SE21628

Reexamination Certificate

active

11279962

ABSTRACT:
A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

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