Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-09-16
1999-11-09
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 30, G01R 3128
Patent
active
059833807
ABSTRACT:
An integrated circuit comprising logic circuits and self-test circuits for testing logic circuits including a pseudo random pattern generator for generating at least one pseudo random pattern and weighing circuit for weighing the pseudo random pattern. The weighting circuit and pseudo random pattern generator generate a plurality of weighted pseudo random patterns including at least one pair of a first weighted pseudo random pattern and a second weighted pseudo random pattern that is the complement of the first pattern. A weighting instruction selects one of the first or second pseudo random patterns for testing the logic circuits.
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"The Weighted Random Test-Pattern Generator," IEEE Transactions on Computers, vol. C-24, No. 7, Jul. 1975, pp. 695-700.
Motika Franco
Pateras Stephen V.
Shushereba John James
Beausoliel, Jr. Robert W.
International Business Machines - Corporation
Iqbal Nadeem
Leas James M.
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